vyges
vyges/mlow-codec
86.975
Overall Score
13
RTL Files
652763
RTL Lines
8
Test Files
0
Gates
N/A
Die Size
📊 Project Overview
MLow: Meta's Low Bitrate Audio Codec - A high-quality, low-complexity audio codec achieving 2x better quality than Opus at 6kbps with 10% lower computational complexity. Implements split-band CELP architecture with SuperWideBand support. Features dual implementation strategy with simplified Icarus-compatible version and full SystemVerilog reference design.
Key Features:
- Core MLow codec functionality
- FPGA-ready implementation
- Open-source toolchain support
- Complete feature set
- Advanced verification capabilities
- Commercial tool support
📋 Available Reports
| Report Name | Description | Actions |
|---|---|---|
| Test Harness Report | Comprehensive test results, simulation analysis, and verification coverage for the IP implementation. | HTML Markdown |
| Code KPIs Report | Code quality metrics, project analysis, and Vyges metadata compliance assessment. | Text JSON |
| Waveform Analysis | VCD waveform analysis for debugging and signal analysis. | 🌊 Waveforms |
| Test Coverage Report | Comprehensive test coverage analysis and verification results. | Text 📊 Coverage |
| Synthesis Results | ASIC and FPGA synthesis reports, resource utilization, and timing analysis. | HTML |
| Gate Analysis Report | Detailed gate-level analysis showing primitive gate counts, transistor estimates, and design complexity metrics. | HTML Markdown |
| FPGA Implementation | Open-source FPGA flow results for various FPGA families. | Markdown |
🔧 Implementation Details
RTL Modules
- range_codec.sv - Range Codec
- celp_decoder.sv - Celp Decoder
- split_band_processor.sv - Split Band Processor
- mlow_codec.sv - Mlow Codec
- celp_encoder.sv - Celp Encoder
- audio_interface.sv - Audio Interface
Testbench Coverage
- SystemVerilog testbenches
- Functional verification
- Performance benchmarking
- Interface testing
🚀 Build Status
| Component | Status | Details |
|---|---|---|
| Simulation | Passing | 15/33 passed (45.5% success rate) Simulators: Icarus Verilog, Verilator, Cocotb |
| Waveforms | Available | VCD files generated for analysis Viewers: GTKWave, Surfer, WaveDrom |
| Synthesis | Clean | Tools: Yosys, OpenLane Technology: Generic, sky130B |
| FPGA Flow | Implemented | Families: iCE40, ECP5, Xilinx 7-series Tools: Yosys, NextPNR, IceStorm |
| Quality Metrics | Ready | Overall Score: 86.975/100 Catalog Ready: Yes | AI Generation Ready: Yes |
Thanks to open-source tools: Verilator, Icarus Verilog, Yosys, GHDL, Netgen, Magic, Python Cocotb, GTKWave, Surfer, KLayout, SkyWater Open PDK, OpenROAD