vyges
vyges/spi-controller
88.8
Overall Score
16
RTL Files
12,567
RTL Lines
9
Test Files
1644
Gates
2.0mm²
Die Size
📊 Project Overview
Serial Peripheral Interface (SPI) master controller supporting all four SPI modes, with APB bus interface, configurable FIFO buffering, and interrupt capabilities. Enables flexible clock polarity/phase, high-speed data transfer, and easy integration into ASIC and FPGA designs
Key Features:
- APB v2.0 compliant interface
- Support for all 4 SPI modes (CPOL/CPHA combinations)
- Configurable FIFO buffering for transmit and receive
- Interrupt generation capabilities
- Configurable baud rate divider
- 8-bit data transfers
- Power management with clock gating
📋 Available Reports
| Report Name | Description | Actions |
|---|---|---|
| Test Harness Report | Comprehensive test results, simulation analysis, and verification coverage for the IP implementation. | HTML Markdown |
| Code KPIs Report | Code quality metrics, project analysis, and Vyges metadata compliance assessment. | Text JSON |
| Waveform Analysis | VCD waveform analysis for debugging and signal analysis. | 🌊 Waveforms |
| Test Coverage Report | Comprehensive test coverage analysis and verification results. | Text 📊 Coverage |
| Synthesis Results | ASIC and FPGA synthesis reports, resource utilization, and timing analysis. | HTML |
| Gate Analysis Report | Detailed gate-level analysis showing primitive gate counts, transistor estimates, and design complexity metrics. | HTML Markdown |
| FPGA Implementation | Open-source FPGA flow results for various FPGA families. | Markdown |
🔧 Implementation Details
RTL Modules
- Top-level module
- Core computation engine
- Control and sequencing
- Memory management
Testbench Coverage
- SystemVerilog testbenches
- Functional verification
- Performance benchmarking
- Interface testing
🚀 Build Status
| Component | Status | Details |
|---|---|---|
| Simulation | Passing | 23/23 passed (100.0% success rate) Simulators: Icarus Verilog, Verilator, Cocotb |
| Waveforms | Available | VCD files generated for analysis Viewers: GTKWave, Surfer, WaveDrom |
| Synthesis | Clean | Tools: Yosys, OpenLane Technology: Generic, sky130B |
| FPGA Flow | Implemented | Families: iCE40, ECP5, Xilinx 7-series Tools: Yosys, NextPNR, IceStorm |
| Quality Metrics | Ready | Overall Score: 88.8/100 Catalog Ready: Yes | AI Generation Ready: Yes |
Thanks to open-source tools: Verilator, Icarus Verilog, Yosys, GHDL, Netgen, Magic, Python Cocotb, GTKWave, Surfer, KLayout, SkyWater Open PDK, OpenROAD