Vyges SPI Controller IP - comprehensive_report

SPI Controller ASIC Synthesis Report

Generated on: Mon Jul 21 03:05:40 UTC 2025

Synthesis Results

SPI Controller Gate-Level Analysis Report

Generated on: 2025-07-21 03:05:40

spi_controller

Total Cells: 1644 Estimated Transistors: 6576

Cell Breakdown

Cell Type	Count	Transistors
ALDFFE_PNP	1	4
ANDNOT	375	1500
AND	29	116
DFFE_PN0P	221	884
DFFE_PN1P	3	12
DFFE_PP	257	1028
DFF_PN0	34	136
MUX	252	1008
NAND	43	172
NOR	11	44
NOT	34	136
ORNOT	49	196
OR	252	1008
XNOR	18	72
XOR	65	260

Summary

Total Cells: 1644 Estimated Total Transistors: 6576

Files Generated

spi_controller_synth.v: Synthesized netlist
spi_controller_synth.json: JSON representation
synthesis.log: Synthesis log

Resource Utilization

Total Cells: 1644
Estimated Transistors: 6576