Vyges

Loom — AI-driven silicon sign-off

A live conformance run on a clean GitHub Actions runner.

Each row is a real chip sign-off engine (timing, power, IR-drop, LVS, thermal, …), run through vyges mcp. The AI agent is handed only a plain-English request and the engines' self-descriptions, and must decide which engine to run and which input to feed it; the engine then executes for real and returns its own content-addressed result. The deterministic column replays known-good calls with no model. The intelligence is in the routing — the ground truth is reproducible without any AI.

When a model is available, it is a stock, general-purpose LLM — no fine-tuning, no training on these tools; it routes purely by reading each engine's self-description at runtime.
The AI column is unavailable. GitHub Models was retired on 30 July 2026 — the endpoint this demo used now returns HTTP 410 for every model, so no model could be reached. We are evaluating replacement providers to bring the live agent-driven demo back. The deterministic column is unaffected: it uses no model, and still runs the real engines end-to-end on a clean runner.
The AI agent (openai/gpt-4.1) could not be reached — no model answered, so this run measured nothing about the engine descriptors. (1 skipped) The deterministic column above is unaffected.
real chip layout
A real taped-out sky130 block (edge-sensor SoC glue), rendered by vyges gds-view — the AI signs off blocks like this below.
Engine · task · inputDeterministic
known-good replay
AI agent
openai/gpt-4.1
⏱️
sta-si
“Run static-timing sign-off on the design described by seq.sta and tell me whether setup and hold timing are met.”
input: seq.sta
PASSFAIL
🕸️
extract
“Extract RC parasitics for the design in counter.ext and report the net count.”
input: counter.ext
PASSFAIL
🖼️
gds-view
“Render the layout in sample.gds to an image.”
input: sample.gds
PASSFAIL
🔍
lvs
“Run LVS for the job in extract.lvs and report whether the layout matches the schematic.”
input: extract.lvs
PASSFAIL
🔋
power
“Estimate power for the design in counter.pwr and report total dynamic power.”
input: counter.pwr
PASSFAIL
em-ir
“Run EM / IR-drop sign-off for the design in block.emir and report whether the IR-drop limit is met.”
input: block.emir
PASSFAIL
🌡️
thermal
“Run thermal analysis for the design in block.thermal and report the peak temperature.”
input: block.thermal
PASSFAIL
〰️
glitch
“Run glitch/hazard analysis on the netlist hazard.v using cells.lib and report the hazard count.”
input: hazard.v, cells.lib
PASSFAIL
🟰
lec
“Run logical-equivalence checking between golden.v and revised_ok.v (using cells.lib) and report whether they are equivalent.”
input: golden.v, revised_ok.v, cells.lib
PASSFAIL
📐
drc
“Run DRC on the layout edge_sensor_glue.gds (a real taped-out sky130 block), with rule deck sky130-min.drc and top cell edge_sensor_glue, and report the violation count.”
input: edge_sensor_glue.gds, sky130-min.drc, edge_sensor_glue
PASSFAIL
🔀
cdc
“Run clock-domain-crossing checks on cdc_demo.v (using cells.lib and cdc_demo.sdc) and report unsynchronized crossings.”
input: cdc_demo.v, cells.lib, cdc_demo.sdc
PASSFAIL
📊
char
“Run characterization for the job and report the model fit.”
input: REPLACE.char
SKIPSKIP
🔧
meas
“Measure the total harmonic distortion of the captured tone in tone.series and tell me whether it meets a -30 dB target. The capture is coherent with the fundamental on DFT bin 16; account for harmonics 2 through 5.”
input: tone.series, 16, thd, 2,3,4,5, -30
PASSFAIL
🔧
opendb
“What is the name of the top-level design block stored in the OpenDB database design.odb?”
input: ['get', '--input', 'design.odb', '--class', 'dbBlock', '--field', 'get_name']
PASSFAIL
🔧
opendb
“I have a 2.5D/3D chiplet assembly described in stack.3dbx. Verify that its die-to-die interfaces really connect — that the bumps on the two mating faces line up and carry the same signals.”
input: ['check-d2d', '--input', 'stack.3dbx']
PASSFAIL
🔧
opendb
“Run the structural checks on the chiplet assembly in stack.odb — overlapping dies, floating dies, bonding-face validity — and tell me how many violations there are.”
input: ['check-3dblox', '--input', 'stack.odb']
PASSFAIL

2026-08-02T06:00:05Z · vyges 0.1.25 (0bf7530) · commit 1e29291 · run log

Vyges Loom — open silicon sign-off you can drive with any model, on your own machine.   Learn more · Talk to us · Reproduce this